CY7C1460SV25

CY7C1462SV25

Document Number: 001-43804 Rev. *J

Page 10 of 31

Partial Write Cycle Description

Partial Write Cycle Description for CY7C1460SV25/CY7C1462SV25 follows. [8, 9, 10, 11]

Function (CY7C1460SV25)

WE

Read

H

X

X

X

X

Write – No bytes written

L

H

H

H

H

H

H

H

L

H

H

L

H

Write Bytes b, a

L

H

H

L

L

H

L

H

H

Write Bytes c, a

L

H

L

H

L

Write Bytes c, b

L

H

LL

L

H

Write Bytes c, b, a

L

H

L

L

L

L

H

H

H

Write Bytes d, a

L

L

H

H

L

Write Bytes d, b

L

LHLH

Write Bytes d, b, a

L

L

H

L

L

Write Bytes d, c

LLL

H

H

Write Bytes d, c, a

L

L

L

H

L

Write Bytes d, c, b

L

L

L

L

H

Write All Bytes

L

L

L

L

L

Function (CY7C1462SV25)

WE

Read

H

X

X

Write – No Bytes Written

L

H

H

H

L

L

H

Write Both Bytes

L

L

L

Notes

8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BWx = L signifies at least one Byte Write Select is active, BWx = Valid

signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

10. When a write cycle is detected, all IOs are tristated, even during byte writes.