OUT

Cell Voltage

V

PROTECT

L

H

t

d

VC2-VC1,

VC1 GND

-

V

HYS

V

8

bq29209-Q1

SLUSC62A – JUNE 2015 – REVISED MARCH 2016

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Feature Description (continued)

If the cell overvoltage condition is removed before the external capacitor reaches the reference voltage, the

internal current source is disabled and an internal discharge block is employed to discharge the external

capacitor down to 0 V. In this instance, the OUT pin remains in a low state.

from a low to a high state, by means of an internal pull-up network, to a regulated voltage of no more than 9.5 V

The external delay capacitor should charge up to no more than the internal LDO voltage (approximately 5 V

typically), and will fully discharge in approximately under 100 ms when the overvoltage condition is removed.

Figure 4. Timing for Overvoltage Sensing

8.3.3 Cell Connection Sequence

NOTE

The recommended cell connection sequence begins from the bottom of the stack, as follows:

1. GND

2. VC1

3. VC2

While not advised, connecting the cells in a sequence other than that described above does not result in errant

activity on the OUT pin. For example:

1. GND

2. VC2 or VC1

3. Remaining VCx pin

8.3.4 Cell Balance Enable Control

To avoid prematurely discharging the cells, it is recommended to turn off (pull high) the active-low Cell Balance

Enable Control pin at lower State of Charge (SOC) levels.