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ATMEGA8515-16AU Datasheet(PDF) 66 Page - ATMEL Corporation |
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ATMEGA8515-16AU Datasheet(HTML) 66 Page - ATMEL Corporation |
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66 / 254 page  66 ATmega8515(L) 2512G–AVR–03/05 Alternate Functions Of Port B The Port B pins with alternate functions are shown in Table 29. The alternate pin configuration is as follows: • SCK – Port B, Bit 7 SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB7. When the pin is forced by the SPI to be an input, the pull-up can still be con- trolled by the PORTB7 bit. • MISO – Port B, Bit 6 MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a Master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a Slave, the data direction of this pin is controlled by DDB6. When the pin is forced by the SPI to be an input, the pull-up can still be con- trolled by the PORTB6 bit. Table 28. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/AD3 PA2/AD2 PA1/AD1 PA0/AD0 PUOE SRE SRE SRE SRE PUOV ~(WR | ADA) • PortA3 ~(WR | ADA) • PortA2 ~(WR | ADA) • PortA1 ~(WR | ADA) • PortA0 DDOE SRE SRE SRE SRE DDOV WR | ADA WR | ADA WR | ADA WR | ADA PVOE SRE SRE SRE SRE PVOV A3 • ADA | D3 OUTPUT • WR A2 • ADA | D2 OUTPUT • WR A1 • ADA | D1 OUTPUT • WR A0 • ADA | D0 OUTPUT • WR DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI D3 INPUTD2 INPUTD1 INPUTD0 INPUT AIO – – – – Table 29. Port B Pins Alternate Functions Port Pin Alternate Functions PB7 SCK (SPI Bus Serial Clock) PB6 MISO (SPI Bus Master Input/Slave Output) PB5 MOSI (SPI Bus Master Output/Slave Input) PB4 SS (SPI Slave Select Input) PB3 AIN1 (Analog Comparator Negative Input) PB2 AIN0 (Analog Comparator Positive Input) PB1 T1 (Timer/Counter1 External Counter Input) PB0 T0 (Timer/Counter0 External Counter Input) OC0 (Timer/Counter0 Output Compare Match Output) |
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