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ATMEGA8515-16AU Datasheet(PDF) 59 Page - ATMEL Corporation |
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ATMEGA8515-16AU Datasheet(HTML) 59 Page - ATMEL Corporation |
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59 / 254 page  59 ATmega8515(L) 2512G–AVR–03/05 Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. Figure 30 shows a functional description of one I/O-port pin, here generically called Pxn. Figure 30. General Digital I/O (1) Note: 1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O, SLEEP, and PUD are common to all ports. Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description for I/O Ports” on page 74, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config- ured as an input pin. If PORTxn is written a logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written a logic zero or the pin has to be configured as an output pin. The port pins are tri-stated when a reset condition becomes active, even if no clocks are running. If PORTxn is written a logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written a logic zero when the pin is configured as an output pin, the port pin is driven low (zero). When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up clk RPx RRx WPx RDx WDx PUD SYNCHRONIZER WDx: WRITE DDRx WPx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN PUD: PULLUP DISABLE clk I/O: I/O CLOCK RDx: READ DDRx D L Q Q RESET RESET Q Q D Q Q D CLR PORTxn Q Q D CLR DDxn PINxn SLEEP SLEEP: SLEEP CONTROL Pxn I/O |
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