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ATMEGA8515-16AU Datasheet(PDF) 56 Page - ATMEL Corporation |
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ATMEGA8515-16AU Datasheet(HTML) 56 Page - ATMEL Corporation |
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56 / 254 page  56 ATmega8515(L) 2512G–AVR–03/05 $C12 out SPH,r16 ; Set Stack Pointer to top of RAM $C13 ldi r16,low(RAMEND) $C14 out SPL,r16 $C15 sei ; Enable interrupts $C16 <instr> xxx Moving Interrupts between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. General Interrupt Control Register – GICR • Bit 1 – IVSEL: Interrupt Vector Select When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the begin- ning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash section is determined by the BOOTSZ Fuses. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 164 for details. To avoid unin- tentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit: 1. Write the Interrupt Vector Change Enable (IVCE) bit to one. 2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE. Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction fol- lowing the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling. Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro- grammed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is pro- gramed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Boot Loader Support – Read-While-Write Self-Programming” on page 164 for details on Boot Lock bits. Bit 7 654 32 10 INT1 INT0 INT2 – – – IVSEL IVCE GICR Read/Write R/W R/W R/W R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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