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ATMEGA8515-16AU Datasheet(PDF) 48 Page - ATMEL Corporation |
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ATMEGA8515-16AU Datasheet(HTML) 48 Page - ATMEL Corporation |
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48 / 254 page  48 ATmega8515(L) 2512G–AVR–03/05 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura- tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period t TOUT. Refer to page 52 for details on operation of the Watchdog Timer. Figure 27. Watchdog Reset During Operation MCU Control and Status Register – MCUCSR The MCU Control and Status Register provides information on which reset source caused an MCU Reset. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 1 – EXTRF: External Reset Flag This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag. • Bit 0 – PORF: Power-on Reset Flag This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then reset the MCUCSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. CK CC Bit 765 432 10 – – SM2 – WDRF BORF EXTRF PORF MCUCSR Read/Write R/W R/W R R/W R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description |
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