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ATMEGA8515-16AU Datasheet(PDF) 41 Page - ATMEL Corporation |
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ATMEGA8515-16AU Datasheet(HTML) 41 Page - ATMEL Corporation |
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41 / 254 page  41 ATmega8515(L) 2512G–AVR–03/05 Extended MCU Control Register – EMCUCR • Bits 7 – SM0: Sleep Mode Select Bit 0 The Sleep Mode Select bits select between the three available sleep modes as shown in Table 16. Note: 1. Standby mode is only available with external crystals or resonators. Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, Timer/Counters, Watchdog, and the Interrupt System to continue operating. This sleep mode basically halts clk CPU and clkFLASH, while allowing the other clocks to run. Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Sta- tus Register – ACSR. This will reduce power consumption in Idle mode. Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the External Interrupts and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, an External level interrupt on INT0 or INT1, or an External interrupt on INT2 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Inter- rupts” on page 76 for details. When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in “Clock Sources” on page 34. Bit 7654 321 0 SM0 SRL2 SRL1 SRL0 SRW01 SRW00 SRW11 ISC2 EMCUCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 000 0 Table 16. Sleep Mode Select SM2 SM1 SM0 Sleep Mode 000 Idle 001 Reserved 010 Power-down 011 Reserved 100 Reserved 101 Reserved 110 Standby(1) 111 Reserved |
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