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ATMEGA8515-16AU Datasheet(PDF) 29 Page - ATMEL Corporation |
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ATMEGA8515-16AU Datasheet(HTML) 29 Page - ATMEL Corporation |
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29 / 254 page  29 ATmega8515(L) 2512G–AVR–03/05 SRAM address space is configured as one sector, the wait states are configured by the SRW11 and SRW10 bits. • Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait State Select Bits for Upper Sector The SRW11 and SRW10 bits control the number of wait states for the upper sector of the External Memory address space, see Table 3. • Bit 3..2 – SRW01, SRW00: Wait State Select Bits for Lower Sector The SRW01 and SRW00 bits control the number of wait states for the lower sector of the External Memory address space, see Table 3. Note: 1. n = 0 or 1 (lower/upper sector). For further details of the timing and wait states of the External Memory Interface, see Figure 13 to Figure 16 how the setting of the SRW bits affects the timing. Table 2. Sector Limits with Different Settings of SRL2..0 SRL2 SRL1 SRL0 Sector Limits 00 0 Lower sector = N/A Upper sector = 0x0260 - 0xFFFF 00 1 Lower sector = 0x0260 - 0x1FFF Upper sector = 0x2000 - 0xFFFF 01 0 Lower sector = 0x0260 - 0x3FFF Upper sector = 0x4000 - 0xFFFF 01 1 Lower sector = 0x0260 - 0x5FFF Upper sector = 0x6000 - 0xFFFF 10 0 Lower sector = 0x0260 - 0x7FFF Upper sector = 0x8000 - 0xFFFF 10 1 Lower sector = 0x0260 - 0x9FFF Upper sector = 0xA000 - 0xFFFF 11 0 Lower sector = 0x0260 - 0xBFFF Upper sector = 0xC000 - 0xFFFF 11 1 Lower sector = 0x0260 - 0xDFFF Upper sector = 0xE000 - 0xFFFF Table 3. Wait States(1) SRWn1 SRWn0 Wait States 0 0 No wait states. 0 1 Wait one cycle during read/write strobe. 1 0 Wait two cycles during read/write strobe. 11 Wait two cycles during read/write and wait one cycle before driving out new address. |
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