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ATMEGA8515-16AU Datasheet(PDF) 90 Page - ATMEL Corporation |
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ATMEGA8515-16AU Datasheet(HTML) 90 Page - ATMEL Corporation |
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90 / 254 page  90 ATmega8515(L) 2512G–AVR–03/05 8-bit Timer/Counter Register Description Timer/Counter Control Register – TCCR0 • Bit 7 – FOC0: Force Output Compare The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate Compare Match is forced on the waveform generation unit. The OC0 output is changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the value present in the COM01:0 bits that determines the effect of the forced compare. A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0 as TOP. The FOC0 bit is always read as zero. • Bit 6, 3 – WGM01:0: Waveform Generation Mode These bits control the counting sequence of the counter, the source for the maximum (TOP) counter value, and what type of waveform generation to be used. Modes of oper- ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table 44 and “Modes of Operation” on page 84. Note: 1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 def- initions. However, the functionality and location of these bits are compatible with previous versions of the timer. • Bit 5:4 – COM01:0: Compare Match Output Mode These bits control the Output Compare pin (OC0) behavior. If one or both of the COM01:0 bits are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corre- sponding to the OC0 pin must be set in order to enable the output driver. Bit 765 432 1 0 FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 TCCR0 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 44. Waveform Generation Mode Bit Description (1) Mode WGM01 (CTC0) WGM00 (PWM0) Timer/Counter Mode of Operation TOP Update of OCR0 at TOV0 Flag Set on 0 0 0 Normal 0xFF Immediate MAX 1 0 1 PWM, Phase Correct 0xFF TOP BOTTOM 2 1 0 CTC OCR0 Immediate MAX 3 1 1 Fast PWM 0xFF TOP MAX |
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