 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
GS1661 Datasheet(PDF) 26 Page - Semtech Corporation |
|
|
|||||||||||||||||||||||||||||
GS1661 Datasheet(HTML) 26 Page - Semtech Corporation |
|
|
26 / 84 page  GS1661 HD/SD SDI Receiver Data Sheet 53751 - 3 September 2012 26 of 84 4.3 Serial Digital Loop-Through Output The GS1661 contains a 100 Ω differential serial output buffer which can be configured to output either a retimed or a buffered version of the serial digital input. The SDO and SDO outputs of this buffer can interface directly to a 1.485Gb/s-capable, SMPTE compliant Gennum cable driver. See 5.3 Typical Application Circuit on page 79. When the RC_BYP pin is set HIGH, the serial digital output is the re-timed version of the serial input. When the RC_BYP pin is set LOW, the serial digital output is simply the buffered version of the serial input, bypassing the internal reclocker. The output can be disabled by setting the SDO_EN/DIS pin LOW. The output is also disabled when the STANDBY pin is asserted HIGH. When the output is disabled, both SDO and SDO pins are set to VDD and remain static. The SDO output is muted when the RC_BYP pin is set HIGH and the PLL is unlocked (LOCKED pin is LOW). When muted, the output is held static at logic ‘0’ or logic ‘1’. NOTE: the serial digital output is muted when the GS1661 is unlocked. 4.4 Serial Digital Reclocker The GS1661 includes both a PLL stage and a sampling stage. The PLL is comprised of two distinct loops: • A coarse frequency acquisition loop sets the centre frequency of the integrated Voltage Controlled Oscillator (VCO) using an external 27MHz reference clock • A fine frequency and phase locked loop aligns the VCO’s phase and frequency to the input serial digital stream The frequency lock loop results in a very fast lock time. The sampling stage re-times the serial digital input with the locked VCO clock. This generates a clean serial digital stream, which may be output on the SDO/SDO output pins and converted to parallel data for further processing. Parallel data is not affected by RC_BYP. Only the SDO is affected by this pin. Table 4-1: Serial Digital Output SDO_EN/DIS RC_BYP SDO/SDO 0X Disabled 11 Re-timed 10 Buffered (not re-timed) |
Similar Part No. - GS1661 |
|
Similar Description - GS1661 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
