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GS1661 Datasheet(PDF) 2 Page - Semtech Corporation |
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GS1661 Datasheet(HTML) 2 Page - Semtech Corporation |
2 / 84 page ![]() GS1661 HD/SD SDI Receiver Data Sheet 53751 - 3 September 2012 2 of 84 packet detection and error handling features. All of these processing features are optional, and may be individually enabled or disabled through register programming. In DVB-ASI mode, sync word detection, alignment and 8b/10b decoding is applied to the received data stream. In Data-Through mode all forms of SMPTE and DVB-ASI processing are disabled, and the device can be used as a simple serial to parallel converter. The device can also operate in a lower power Standby mode. In this mode, no signal processing is carried out and the parallel output is held static. Parallel data outputs are provided in 20-bit or 10-bit format for HD and SD video rates, with a variety of mapping options. As such, this parallel bus can interface directly with video processor ICs, and output data can be multiplexed onto 10 bits for a low pin count interface. Functional Block Diagram GS1661 Functional Block Diagram Revision History Buffer Mux Reclocker with Integrated VCO SDI SDO SDO Serial to Parallel Converter Descramble, Word Align, Rate Detect Flywheel Video Standard Detect TRS Detect Timing Extraction Mux DVB-ASI Decoder Illegal code remap, TRS/ Line Number/ CRS Insertion, EDH Packet Insertion ANC/ Checksum /352M Extraction GSPI and JTAG Controller Host Interface Output Mux/ Demux Crystal Buffer/ Oscillator LF LB_CONT VBG I/O Control Buffer SDI NGEN EQ AGC+ AGC- DOUT[19:0] PCLK LOCKED Version ECR PCN Date Changes and/or Modifications 3 158468– September 2012 Changes throughout the document. 2 153968 – April 2010 Removed VCO Supply Voltage from Table 2-2: Recommended Operating Conditions, and revised VCO_VDD Pin Description in Table 1-1: Pin Descriptions. 1 153472 – January 2010 Converted to Data Sheet. 0 152960– November 2009 New Document. Added reference to GS1660/GS1661 Errata (document number 53877). |
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