 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
GS1661 Datasheet(PDF) 12 Page - Semtech Corporation |
|
||||||||||||||||||||||||||||||
GS1661 Datasheet(HTML) 12 Page - Semtech Corporation |
|
|
12 / 84 page  GS1661 HD/SD SDI Receiver Data Sheet 53751 - 3 September 2012 12 of 84 G8DVB_ASI Input/Output CONTROL SIGNAL INPUT Please refer to the Input/Output Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to enable/disable DVB-ASI data extraction in manual mode. When the AUTO/MAN bit in the host interface is LOW, this pin is an input and when the DVB_ASI pin is set HIGH the device will carry out DVB_ASI data extraction and processing. The SMPTE_BYPASS pin must be set LOW. When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in Data-Through mode. When the AUTO/MAN bit in the host interface is HIGH (default), DVB-ASI is configured as a status output (set LOW), and DVB-ASI input streams are not supported or recognized. H1 BUFF_VDD Input Power POWER pin for the serial digital output 50 Ω buffer. Connect to 3.3V DC analog. H2 BUFF_GND Input Power GND pin for the cable driver buffer. Connect to analog GND. H5 TIM_861 Input CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to select CEA-861 timing mode. When TIM_861 is HIGH, the device outputs CEA 861 timing signals (HSYNC/VSYNC/DE) instead of H:V:F digital timing signals. H6 XTAL_OUT Digital Output Buffered 27MHz crystal output. Can be used to cascade the crystal signal. H7 20bit/10bit Input CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to select the output bus width. HIGH = 20-bit, LOW = 10-bit. H8 IOPROC_EN/DIS Input CONTROL SIGNAL INPUT Please refer to the Input Logic parameters in the DC Electrical Characteristics table for logic level threshold and compatibility. Used to enable or disable video processing features. When IOPROC_EN is HIGH, the video processing features of the device are enabled. When IOPROC_EN is LOW, the processing features of the device are disabled, and the device is in a low-latency operating mode. J1, K1 SDO, SDO Output Serial Data Output Signal. 50 Ω CML buffer for interfacing to an external cable driver. Serial digital output signal operating at 1.485Gb/s, 1.485/1.001Gb/s and 270Mb/s. Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description |
Similar Part No. - GS1661 |
|
Similar Description - GS1661 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
