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GS1661 Datasheet(PDF) 74 Page - Semtech Corporation |
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GS1661 Datasheet(HTML) 74 Page - Semtech Corporation |
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74 / 84 page  GS1661 HD/SD SDI Receiver Data Sheet 53751 - 3 September 2012 74 of 84 037h ERROR_MASK_1 RSVD 15-11 Reserved. R 0 ERROR_MASK_1 10-0 Error mask for global error vector (HD, SD): bit[0]: EAV_ERR_DS1 mask bit[1]: SAV_ERR_DS1 mask bit[2]: LNUM_ERR_DS1 mask bit[3]: YCRC_ERR_DS1 mask bit[4]: CCRC_ERR_DS1 mask bit[5]: YCS_ERR_DS1 mask bit[6]: CCS_ERR_DS1 mask bit[7]: Reserved bit[8]: AP_CRC_ERR mask bit[9]: FF_CRC_ERR mask bit[10]: VD_STD_ERR_DS1 mask R/W 0 038h - 6Bh RSVD RSVD 15-0 Reserved. R 0 06Ch CLK_GEN RSVD 15-5 Reserved. R/W 0 DEL_LINE_OFFSET 4-0 Controls the offset for the delay line. R/W 0 06Dh IO_DRIVE _STRENGTH RSVD 15-6 Reserved. R/W 0 IO_DS_CTRL_DOUT_MSB 5-4 Drive strength adjustment for DOUT[19:10] outputs and PCLK output: 00: 4mA; 01: 8mA; 10: 10mA(1.8V), 12mA(3.3V); 11: 12mA(1.8V), 16mA(3.3V) R/W 2 IO_DS_CTRL_STAT 3-2 Drive strength adjustment for STAT[5:0] outputs: 00: 4mA; 01: 6mA; 10: 8mA(1.8V), 10mA(3.3V); 11: 10mA(1.8V), 12mA(3.3V) R/W 2 IO_DS_CTRL_DOUT_LSB 1-0 Drive strength adjustment for DOUT[9:0] outputs: 00: 4mA; 01: 6mA; 10: 8mA(1.8V), 10mA(3.3V); 11: 10mA(1.8V), 12mA(3.3V) R/W 3 06Eh - 072h RSVD RSVD − Reserved. R/W 0 073h EQ_BYPASS RSVD 15-10 Reserved. R/W 0 EQ_BYPASS 9 0: non-bypass EQ 1: bypass EQ R/W 0 RSVD 8-0 Reserved. R/W 0 074h -085h RSVD RSVD 15-0 Reserved. R/W 0 Table 4-17: Configuration and Status Registers (Continued) Address Register Name Bit Name Bit Description R/W Default |
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