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GS1661 Datasheet(PDF) 73 Page - Semtech Corporation |
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GS1661 Datasheet(HTML) 73 Page - Semtech Corporation |
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73 / 84 page  GS1661 HD/SD SDI Receiver Data Sheet 53751 - 3 September 2012 73 of 84 022h RASTER_STRUC_ 4 RATE_SEL_READBACK 15-14 Read back detected data rate: 0 = HD, 1,3=SD, 2=Reserved R0 M13 Specifies detected M value 0: 1.000 1: 1.001 R0 Note: In certain systems, due to the greater ppm offsets in the crystal, the ‘M’ bit may not assert properly. In such cases, bits 3:0 in Register 06Fh can be increased to a maximum value of 4. STD_LOCK12 Video standard lock. R 0 INT_PROG 11 Interlaced or progressive. R 0 ACTLINE_PER_FIELD 10-0 Active lines per frame. R 0 023h FLYWHEEL _STATUS RSVD 15-2 Reserved. R 0 V_LOCK_DS11 Indicates that the timing signal generator is locked to vertical timing (HD and SD inputs). R0 H_LOCK_DS10 Indicates that the timing signal generator is locked to horizontal timing (HD and SD inputs). R0 024h RATE_SEL RSVD 15-3 Reserved. R 0 AUTO/MAN 2Detect data rate automatically (1) or program manually (0). R/W 1 RATE_SEL_TOP 1-0 Programmable rate select in manual mode: 0 = HD, 1,3=SD, 2=Reserved R/W 0 025h TIM_861_ FORMAT RSVD 15-7 Reserved. R 0 FORMAT_ERR 6 Indicates standard is not recognized for CEA 861 conversion. R1 FORMAT_ID_8615-0 CEA-861 format ID of input video stream. Refer to Table 4-9. R0 026hTIM_861_CFG RSVD 15-3 Reserved. R 0 VSYNC_INVERT 2 Invert output VSYNC pulse. R/W 0 HSYNC_INVERT 1 Invert output HSYNC pulse. R/W 0 TRS_8610 Sets the timing reference outputs to DFP timing mode when set to '1'. By default, the timing reference outputs follow CEA-861 timing mode. Only valid when TIM_861 is set to '1'. R/W 0 027h - 036h RSVD RSVD − Reserved. R 0 Table 4-17: Configuration and Status Registers (Continued) Address Register Name Bit Name Bit Description R/W Default |
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