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GS1661 Datasheet(PDF) 39 Page - Semtech Corporation

Part # GS1661
Description  HD/SD SDI Receiver, with Integrated Adaptive Cable Equalizer complete with SMPTE Video Processing
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Manufacturer  SEMTECH [Semtech Corporation]
Direct Link  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

GS1661 Datasheet(HTML) 39 Page - Semtech Corporation

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GS1661 HD/SD SDI Receiver
Data Sheet
53751 - 3
September 2012
39 of 84
4.11 H:V:F Timing Signal Generation
The GS1661 extracts critical timing parameters from the received TRS words.
Horizontal blanking (H), Vertical blanking (V), and Field odd/even (F) timing are output
on the STAT[2:0] pins by default.
Using the H_CONFIG bit in the host interface, the H signal timing can be selected as one
of the following:
1. Active line blanking (H_CONFIG = LOW) - the H output is HIGH for the horizontal
blanking period, including the EAV TRS words.
2. TRS based blanking (H_CONFIG = HIGH) - the H output is set HIGH for the entire
horizontal blanking period as indicated by the H bit in the received TRS signals.
The timing of these signals is shown in Figure 4-8 below.
NOTE: Both 8-bit and 10-bit TRS words are identified by the device.
Figure 4-6: H:V:F Output Timing - HDTV 20-bit Mode
Figure 4-7: H:V:F Output Timing - HDTV 10-bit Mode
VIDEO ERROR
0111
EDH DETECTED
1001
CARRIER DETECT
1010
RATE_DET
1011
NOTE:
Each of the STAT[5:0] pins are configurable individually using the register bits in the host interface; STAT[5:0]_CONFIG (008h/009h).
Table 4-8: Output Signals Available on Programmable Multi-Function Pins (Continued)
Status Signal
Selection Code
Default Output Pin
PCLK
LUMA DATA
CHROMA DATA
H
000
000
3FF
000
000
3FF
V
F
XYZ (SAV)
000
000
3FF
000
000
3FF
XYZ (SAV)
XYZ (EAV)
XYZ (EAV)
000
000
3FF
3FF
000
000
PCLK (HD)
H
V
F
MULTIPLEXED Y’CbCr DATA (HD)
000
000
3FF
3FF
000
000
XYZ (EAV)
MULTIPLEXED Y’CbCr DATA (HD)
H
V
F
PCLK (HD)
H S IGN A L T IM IN G :
H_ C O NF IG = L O W
H _ C ONF IG = H IGH
HVF T IM IN GAT SAV
HVF T IM IN GAT EAV
XYZ (EAV)
XYZ (SAV)
XYZ (SAV)


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