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GS1661 Datasheet(PDF) 34 Page - Semtech Corporation |
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GS1661 Datasheet(HTML) 34 Page - Semtech Corporation |
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34 / 84 page  GS1661 HD/SD SDI Receiver Data Sheet 53751 - 3 September 2012 34 of 84 WORDERR is HIGH whenever the device has detected a running disparity error or illegal code word. 4.8.4 Parallel Output in Data-Through Mode This mode is enabled when the SMPTE_BYPASS and DVB_ASI pins are LOW. In this mode, data is passed to the output bus without any decoding, descrambling or word-alignment. The output data width (10-bit or 20-bit) is controlled by the setting of the 20bit/10bit pin. 4.8.5 Parallel Output Clock (PCLK) The frequency of the PCLK output signal of the GS1661 is determined by the output data rate and the 20bit/10bit pin setting. Table 4-6 lists the output signal formats according to the data format selected in Manual mode (AUTO/MAN bit in the host interface is set LOW), or detected in Auto Mode (AUTO/MAN bit in the host interface is set HIGH). Table 4-6: GS1661 PCLK Output Rates Output Data Format Pin/Control Bit Settings PCLK Rate 20bit/ 10bit RATE_DET SMPTE_ BYPASS DVB-ASI 20-bit demultiplexed HD format HIGHLOW HIGH LOW 74.25 or 74.25/1.001MHz 20-bit data output HD format HIGH LOW LOW LOW 74.25 or 74.25/1.001MHz 20-bit demultiplexed SD format HIGHHIGHHIGH LOW 13.5MHz 20-bit data output SD format HIGHHIGH LOW LOW 13.5MHz 10-bit multiplexed HD format LOW LOW HIGH LOW 148.5 or 148.5/1.001MHz 10-bit data output HD format LOW LOW LOW LOW 148.5 or 148.5/1.001MHz 10-bit multiplexed SD format LOW HIGHHIGH LOW 27MHz 10-bit data output SD format LOW HIGH LOW LOW 27MHz 10-bit ASI output SD format LOW HIGHLOW HIGH 27MHz |
Similar Part No. - GS1661 |
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Similar Description - GS1661 |
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