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RM46L830 Datasheet(PDF) 5 Page - Texas Instruments |
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RM46L830 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 179 page  RM46L430, RM46L830 www.ti.com SPNS182C – SEPTEMBER 2012 – REVISED JUNE 2015 Table of Contents 1 Device Overview ......................................... 1 6.10 Flash Memory ....................................... 83 1.1 Features .............................................. 1 6.11 Tightly Coupled RAM Interface Module ............. 86 1.2 Applications ........................................... 2 6.12 Parity Protection for Accesses to Peripheral RAMs 86 1.3 Description ............................................ 2 6.13 On-Chip SRAM Initialization and Testing ........... 88 1.4 Functional Block Diagram ............................ 4 6.14 External Memory Interface (EMIF) .................. 90 2 Revision History ......................................... 6 6.15 Vectored Interrupt Manager ......................... 98 3 Device Comparison ..................................... 7 6.16 DMA Controller ..................................... 102 4 Terminal Configuration and Functions ............. 8 6.17 Real Time Interrupt Module ........................ 105 4.1 PGE QFP Package Pinout (144-Pin) ................. 8 6.18 Error Signaling Module ............................. 107 4.2 ZWT BGA Package Ball-Map (337 Ball Grid Array) .. 9 6.19 Reset / Abort / Error Sources ...................... 111 4.3 Terminal Functions ................................. 10 6.20 Digital Windowed Watchdog ....................... 114 5 Specifications .......................................... 48 6.21 Debug Subsystem ................................. 115 5.1 Absolute Maximum Ratings Over Operating Free- 7 Peripheral Information and Electrical Air Temperature Range ............................ 48 Specifications ......................................... 120 5.2 ESD Ratings ........................................ 48 7.1 Enhanced Translator PWM Modules (ePWM) ..... 120 5.3 Power-On Hours (POH) ............................. 48 7.2 Enhanced Capture Modules (eCAP) ............... 125 5.4 Device Recommended Operating Conditions ....... 49 7.3 Enhanced Quadrature Encoder (eQEP) ........... 127 5.5 Switching Characteristics Over Recommended 7.4 Multibuffered 12bit Analog-to-Digital Converter .... 128 Operating Conditions for Clock Domains ........... 50 7.5 General-Purpose Input/Output ..................... 140 5.6 Wait States Required ............................... 50 7.6 Enhanced High-End Timer (N2HET) .............. 141 5.7 Power Consumption Over Recommended 7.7 Controller Area Network (DCAN) .................. 145 Operating Conditions ................................ 51 7.8 Local Interconnect Network Interface (LIN) ........ 146 5.8 Input/Output Electrical Characteristics Over 7.9 Serial Communication Interface (SCI) ............. 147 Recommended Operating Conditions ............... 52 7.10 Inter-Integrated Circuit (I2C) ....................... 148 5.9 Thermal Resistance Characteristics ................ 52 7.11 Multibuffered / Standard Serial Peripheral 5.10 Output Buffer Drive Strengths ...................... 53 Interface ............................................ 151 5.11 Input Timings ........................................ 54 7.12 Universal Serial Bus (USB) Host and Device 5.12 Output Timings ...................................... 54 Controllers ......................................... 163 5.13 Low-EMI Output Buffers ............................ 56 8 Device and Documentation Support .............. 165 6 System Information and Electrical 8.1 Device and Development-Support Tool Specifications ........................................... 57 Nomenclature ...................................... 165 6.1 Device Power Domains ............................. 57 8.2 Documentation Support ............................ 166 6.2 Voltage Monitor Characteristics ..................... 57 8.3 Trademarks ........................................ 166 6.3 Power Sequencing and Power On Reset ........... 59 8.4 Electrostatic Discharge Caution ................... 166 6.4 Warm Reset (nRST) ................................. 61 8.5 Glossary ............................................ 166 6.5 ARM Cortex-R4F CPU Information ................. 62 8.6 Device Identification ................................ 167 6.6 Clocks ............................................... 65 8.7 Module Certifications ............................... 169 6.7 Clock Monitoring .................................... 73 9 Mechanical Packaging and Orderable 6.8 Glitch Filters ......................................... 75 Information ............................................. 174 6.9 Device Memory Map ................................ 76 9.1 Packaging Information ............................. 174 Copyright © 2012–2015, Texas Instruments Incorporated Table of Contents 5 Submit Documentation Feedback Product Folder Links: RM46L430 RM46L830 |
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