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SN74LVC1G86DCKTG4 Datasheet(PDF) 8 Page - Texas Instruments |
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SN74LVC1G86DCKTG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 24 page = 1 EXCLUSIVE OR SN74LVC1G86 SCES222P – APRIL 1999 – REVISED SEPTEMBER 2015 www.ti.com 8 Detailed Description 8.1 Overview The SN74LVC1G86 device performs the Boolean function Y = A × B or Y = AB + AB in positive logic. This single 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation. A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output. NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. 8.2 Functional Block Diagram These are five equivalent exclusive-OR symbols valid for an SN74LVC1G86 gate in positive logic; negation may be shown at any two ports. 8.3 Feature Description SN74LVC1G86 has a wide operating voltage range from 1.65 V to 5.5 V.This allows down voltage translation and also accepts inputs voltages to 5.5 V. The maximum propagation delay is 4n s at 3.3 V at 15-pF capacitor load. Power consumption is low with 10 µA maximum Icc current. It supports ±24-mA output drive at 3.3 V. The SN74LVC1G86 is specified for partial power down applications using Ioff supporting Live insertion and Back-Drive protection. 8.4 Function Table Table 1 lists the functional modes of the SN74LVC1G86. Table 1. Function Table INPUTS OUTPUT Y A B L L L L H H H L H H H L 8 Submit Documentation Feedback Copyright © 1999–2015, Texas Instruments Incorporated Product Folder Links: SN74LVC1G86 |
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