RETIMER / FIFO

VCO / PLL

SDI0

LOCK DETECT

SDO

CONTROL LOGIC

AUTO BYPASS

BYPASS/

O/P MUTE

RATE0

RATE1

50

50

XTAL IN/EXT CLK

XTAL OUT

LOOP FILTER 1

LOOP FILTER 2

SCO_EN

SCO/SDO2

BYPASS

SDI0

SDO

50

50

SD/ HD

SCO/SDO2

SDI1

SDI1

SDI2

SDI2

SDI3

SDI3

SEL0

SEL1

ENABLE

EQUALIZER

EQUALIZER

EQUALIZER

EQUALIZER

10

LMH0356

SNLS270L – AUGUST 2007 – REVISED JANUARY 2016

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Product Folder Links: LMH0356

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Copyright © 2007–2016, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The LMH0356 3-Gbps HD/SD SDI Reclocker with 4:1 Input Mux and FR4 EQs is used in many types of digital

video signal processing equipment. Supported serial digital video standards are ST-259, ST-292, and ST-424.

Corresponding serial data rates are 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. DVB-ASI

data at 270 Mbps may also be retimed. The LMH0356 retimes the serial data stream to suppress accumulated

jitter. It provides two low-jitter, differential, serial data outputs. The second output may be selected to output

either serial data or a low-jitter serial data-rate clock. Controls and indicators are: serial clock or second serial

data output select, manual rate select input, SD/HD rate output, lock detect output, auto/manual data bypass and

output mute.

Serial data inputs are CML and LVPECL compatible. Serial data and clock outputs are differential CML and

produce LVPECL compatible levels. The output buffer design can drive AC or DC-coupled, terminated 100-

Ω

inputs and outputs are LVCMOS compatible.

The device package is a 48-pin WQFN or a 40-pin WQFN. Both package options have an exposed die attach

terminal for the device. This terminal must be connected to the negative power supply or circuit ground.

8.2 Functional Block Diagram