LMH0356

SDI0

SDI0

1

2

3

4

5

6

7

8

9

10

11

12

25

26

27

28

29

30

31

32

33

34

SCO/SDO2

SCO/SDO2

SDO

SDO

HD

SD/

SDI1

SDI1

SDI2

SDI2

SDI3

SDI3

ENABLE

35

36

DAP

Differential

Data Input 3

Differential

Data Input 2

Differential

Data Input 1

Differential

Data Input 0

ENABLE

27 MHz

39 pF

39 pF

Data

Output

Clock Output or

2

HD

SD/

56 nF

LOCK DET

MUTE

BYPASS/AUTO BP

SEL1

SEL0

RATE1

RATE0

SCO_EN

OP

16

LMH0356

SNLS270L – AUGUST 2007 – REVISED JANUARY 2016

www.ti.com

Product Folder Links: LMH0356

Submit Documentation Feedback

Copyright © 2007–2016, Texas Instruments Incorporated

Typical Application (continued)

Figure 5. Application Circuit

ENABLE has an internal pullup to enable the device by default. This pin may be pulled low to put the LMH0356

into a powered down mode.

BP/AUTO BP has an internal pulldown to enable Auto Bypass mode by default. This pin may be pulled high to

force the LMH0356 to bypass all data.

OP MUTE has an internal pullup to enable the outputs by default. This pin may be pulled low to mute the

outputs.

The XTAL IN/EXT CLK and XTAL OUT pins are shown with a 27-MHz crystal and the proper loading. The crystal

should match the parameters described in Table 4. Alternately, a 27-MHz LVCMOS compatible clock signal may

be input to XTAL IN/EXT CLK.

The active high LOCK DET output provides an indication that proper data is being received and the PLL is

locked.

The SD/HD output may be used to drive the SD/HD pin of an SDI cable driver (such as the LMH0302) in order to

properly set the cable driver’s edge rate for SMPTE compliance. It defaults to HD/3G (low) when the LMH0356 is

not locked.