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LMH0356 Datasheet(PDF) 9 Page - Texas Instruments |
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LMH0356 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 28 page  SDI 270 MBPS DATA NO DATA T2 1485 MBPS DATA 2970 MBPS DATA 270 MBPS DATA T1 TACQ T2 T2 SDI 270 MBPS DATA NO DATA Lock Dete ct SD/HD T2 NO DATA 1485 MBPS DATA NO DATA T2 Lock Dete ct SD/HD T1 TACQ T1 TACQ TACQ T1 TACQ T1 T1 TACQ T1 T1 9 LMH0356 www.ti.com SNLS270L – AUGUST 2007 – REVISED JANUARY 2016 Product Folder Links: LMH0356 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated (1) Measured from first SDI transition until Lock Detect output goes high (true). (2) This specification is ensured by design. (3) RL = 100-Ω differential. (4) This parameter is ensured by characterization over voltage and temperature limits. 7.7 AC Timing Requirements MIN NOM MAX UNIT TACQ Acquisition time See (1) 15 ms tr, tf Logic inputs rise/fall time 10%–90% 1.5 ns tr, tf Input rise/fall time 20%–80%, 270 Mbps (2) 1500 ps tr, tf Input rise/fall time 20%–80%, 1483 or 1485 Mbps (2) 270 ps tr, tf Input rise/fall time 20%–80%, 2967 or 2970 Mbps (2) 135 ps tr, tf Logic outputs rise/fall time 10%–90% 1.5 ns tr, tf Output rise/fall time 20%–80% (3) (4) 90 130 ps TACQ = Acquisition Time, defined in AC Timing Requirements T1 = Time from Lock Detect assertion or deassertion until SD/HD output is valid, typically 37 ns (one 27-MHz clock period) T2 = Time from SDI input change until Lock Detect deassertion, 1 ms maximum. SD/HD output is not valid during this time. Figure 1. SDI, Lock Detect, and SD/HD Timing |
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