37

38

39

40

41

42

43

44

45

46

47

48

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

25

26

27

28

29

30

31

32

33

34

35

36

56 nF

SDI0

SDI0

____

SDI1

____

SDI2

____

SDI3

____

SDI1

SDI2

SDI3

SD0

SD0

___

_

SC0/SDO2

SC0/SDO2

________

20

LMH0356

SNLS270L – AUGUST 2007 – REVISED JANUARY 2016

www.ti.com

Product Folder Links: LMH0356

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Copyright © 2007–2016, Texas Instruments Incorporated

11 Layout

11.1 Layout Guidelines

Figure 11 shows a typical PCB layout for the 48-pin WQFN version of the LMH0356. The following guidelines are

recommended for designing the board layout for the LMH0356:

1. Choose a suitable board stack-up such that it supports 100-

Ω differential trace routing on board layer 1. This

is typically done with layer 2 ground plane reference for the 100-

Ω differential traces.

2. Place 56-nF loop filter capacitor as close to the loop filter pins as possible.

3. Use coupled differential traces with 100-

Ω ± 5% impedance for signal routing to SDI± and SDO± pins. These

are usually 5 to 8-mil trace width reference to a ground plane at layer 2.

4. DAP of the package must be connected to the ground plane through an array of via. These nine vias are

solder-masked to avoid solder flowing into the plated-through holes during the board manufacturing process.

DAP is divided into 16 squares (1.09 mm × 1.09 mm) inside 5.1-mm × 5.1-mm landing pad.

tangent to the supply pin landing pad with the shortest trace possible.

6. Power supply bypass capacitors must be placed close to the supply pin. They are commonly placed at the

bottom layer sharing the ground connector of the DAP.

11.2 Layout Example

Figure 11 shows a typical PCB layout for the 48-pin WQFN version of the LMH0356.

Figure 11. LMH0356 PCB Layout Example