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LMH0356 Datasheet(PDF) 17 Page - Texas Instruments |
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LMH0356 Datasheet(HTML) 17 Page - Texas Instruments |
17 / 28 page ![]() 17 LMH0356 www.ti.com SNLS270L – AUGUST 2007 – REVISED JANUARY 2016 Product Folder Links: LMH0356 Submit Documentation Feedback Copyright © 2007–2016, Texas Instruments Incorporated Typical Application (continued) SCO_EN has an internal pulldown to set the second output (SCO/SDO2) to output data. This pin may be pulled high to set the second output as a serial clock. The external loop filter capacitor (between LF1 and LF2) must be 56 nF. This is the only supported value; the loop filter capacitor must not be changed. RATE0 and RATE1 have internal pulldowns to select Auto-Rate Detect mode by default. These pins may also be used to set the device to SD mode or HD/3G mode. SEL0 and SEL1 have internal pulldowns to select the SDI0 input by default. 9.2.1 Design Requirements For this design example, use the parameters listed in Table 5 as the input parameters. Table 5. LMH0356 Design Parameters DESIGN PARAMETER REQUIREMENTS Input AC-coupling capacitors The user should check output common mode voltage of the device attached to SDI pins. If AC-coupling capacitor is required, AC-coupling capacitor is expected to be 4.7 μF ±10%. Refer to Input Output Interfacing for details. Output AC-coupling capacitors The user should check input common mode voltage of the device attached to SDO pins. If AC-coupling capacitor is required, AC-coupling capacitor is expected to be 4.7 μF ±10%. Refer to Input Output Interfacing for details. DC power supply coupling capacitors De-coupling capacitors are required to minimize power supply ripple noise. Place 4.7- μF and 0.1-μF surface mount ceramic capacitors as close to the device VCC pin as possible . High-speed SDI and SDO trace impedance SDI± and SDO± must be routed with coupled board traces with 100- Ω ± 5% differential impedance. Use of ENABLE, RATE0/1, SCO_EN, OP MUTE, and BP/AUTO BP pins Set these pins for desired operating mode. LOCK DET pin Use this pin for lock indication or to OP MUTE pin to enable output when locked. SD/HD Pin Use SD/HD to set cable driver edge rate or to FPGA for lock rate monitoring. 9.2.2 Detailed Design Procedure To begin the design process, determine the following: 1. Check that the power supply meets the DC and AC requirements in DC Electrical Characteristics. 2. Select the proper pull-high or pull-low resistors for ENABLE, RATE0/1, SCO_EN, OP MUTE, and BP/AUTO BP pins. 3. Use SD/HD output signal to set the cable driver edge rate. 4. Refer to Input Output Interfacing for Input or Output DC- or AC-coupling. 5. Choose small 0402 surface mount ceramic capacitors for AC-coupling and bypass capacitors. 6. Pay close attention to high speed printed circuit board layout for the high speed SDI± and SDO± signals. 7. Plan out overall system jitter budget with AC Electrical Characteristics in mind. 9.2.2.1 Input Output Interfacing The inputs are LVPECL compatible. The LMH0356 has a wide input common mode range, and in most cases the input should be DC-coupled. For DC-coupling, the inputs must be kept within the common mode range specified in DC Electrical Characteristics. Figure 6 shows an example of a DC-coupled interface between the LMH0344 cable equalizer and the LMH0356. The LMH0344 output common mode voltage and voltage swing are within the range of the input common mode voltage and voltage swing of the LMH0356. In this figure, the LMH0344 cable equalizer restores the signal after the coaxial cable. The LMH0356 FR4 equalizer restores the signal after the loss due to the FR4 trace. The LMH0356 inputs have 50- Ω internal terminations (100-Ω differential) to terminate the transmission line, so no additional components are required. |
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