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ADS41B29 Datasheet(PDF) 1 Page - Texas Instruments |
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ADS41B29 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 59 page  14-Bit ADC OVR_SDOUT D10_D11_M D10_D11_P D8_D9_M D8_D9_P D6_D7_M D6_D7_P D4_D5_M D4_D5_P D2_D3_M D2_D3_P D0_D1_M D0_D1_P CLKOUTM CLKOUTP CLKM CLKP CLOCKGEN INM VCM INP Sampling Circuit Common DigitalFunctions DDR Serializer Reference OE Control Interface ADS41B49 AVDD AGND DRVDD DRGND DDRLVDS Interface D12_D13_M D12_D13_P AnalogBuffers AVDD_BUF Product Folder Sample & Buy Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. ADS41B29, ADS41B49 SBAS486F – NOVEMBER 2009 – REVISED FEBRUARY 2016 ADS41Bx9 14- and 12-Bit, 250-MSPS, Ultralow-Power ADCs with Analog Buffers 1 1 Features 1 • ADS41B49: 14-Bit, 250 MSPS ADS41B29: 12-Bit, 250 MSPS • Integrated High-Impedance Analog Input Buffer: – Input Capacitance: 2 pF – 200-MHz Input Resistance: 3 k Ω • Maximum Sample Rate: 250 MSPS • Ultralow Power: – 1.8-V Analog Power: 180 mW – 3.3-V Buffer Power: 96 mW – I/O Power: 135 mW (DDR LVDS) • High Dynamic Performance: – SNR: 69 dBFS at 170 MHz – SFDR: 82.5 dBc at 170 MHz • Output Interface: – Double Data Rate (DDR) LVDS with Programmable Swing and Strength: – Standard Swing: 350 mV – Low Swing: 200 mV – Default Strength: 100- Ω Termination – 2x Strength: 50- Ω Termination – 1.8-V Parallel CMOS Interface Also Supported • Programmable Gain for SNR, SFDR Trade-Off • DC Offset Correction • Supports Low Input Clock Amplitude • Package: VQFN-48 (7 mm × 7 mm) 2 Applications • Power Amplifier Linearization • Software Defined Radio • Wireless Communications Infrastructure 3 Description The ADS41Bx9 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, and consume extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization. The ADS41Bx9 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance. The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500 MBPS) makes using low-cost field-programmable gate array (FPGA)-based receivers possible. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50- Ω differential termination. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) ADS41Bx9 VQFN (48) 7.00 mm × 7.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. ADS41B49 Block Diagram |
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