R

R

R

GND

TRIGGER

OUTPUT

RESET

1

2

3

4

DISCHARGE

THRESHOLD

CONTROL

VOLTAGE

8

7

6

5

COMPAR-

ATOR

COMPAR-

ATOR

FLIP FLOP

OUTPUT

STAGE

VREF (INT)

LM555

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SNAS548D – FEBRUARY 2000 – REVISED JANUARY 2015

5 Pin Configuration and Functions

D, P, and DGK Packages

8-Pin PDIP, SOIC, and VSSOP

Top View

Pin Functions

PIN

I/O

DESCRIPTION

NO.

NAME

Control

Controls the threshold and trigger levels. It determines the pulse width of the output

5

Voltage

I

waveform. An external voltage applied to this pin can also be used to modulate the output

waveform

Discharge

Open collector output which discharges a capacitor between intervals (in phase with output).

7

I

It toggles the output from high to low when voltage reaches 2/3 of the supply voltage

1

GND

O

Ground reference voltage

3

Output

O

Output driven waveform

Reset

Negative pulse applied to this pin to disable or reset the timer. When not used for reset

4

I

purposes, it should be connected to VCC to avoid false triggering

Threshold

Compares the voltage applied to the terminal with a reference voltage of 2/3 Vcc. The

6

I

amplitude of voltage applied to this terminal is responsible for the set state of the flip-flop

Trigger

Responsible for transition of the flip-flop from set to reset. The output of the timer depends

2

I

on the amplitude of the external trigger pulse applied to this pin

8

I

Supply voltage with respect to GND

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