LM555

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SNAS548D – FEBRUARY 2000 – REVISED JANUARY 2015

9 Power Supply Recommendations

The LM555 requires a voltage supply within 4.5 V to 16 V. Adequate power supply bypassing is necessary to

protect associated circuitry. The minimum recommended capacitor value is 0.1

μF in parallel with a 1-μF

electrolytic capacitor. Place the bypass capacitors as close as possible to the LM555 and minimize the trace

length.

10 Layout

10.1 Layout Guidelines

Standard PCB rules apply to routing the LM555. The 0.1-µF capacitor in parallel with a 1-µF electrolytic capacitor

should be as close as possible to the LM555. The capacitor used for the time delay should also be placed as

close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity and

signal integrity.

Figure 20 is the basic layout for various applications.

•

C1 – based on time delay calculations

•

C2 – 0.01-µF bypass capacitor for control voltage pin

•

C3 – 0.1-µF bypass ceramic capacitor

•

C4 – 1-µF electrolytic bypass capacitor

•

R1 – based on time delay calculations

•

U1 – LMC555

10.2 Layout Example

Figure 20. Layout Example

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