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CDCM6208V1FRGZR Datasheet(PDF) 13 Page - Texas Instruments |
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CDCM6208V1FRGZR Datasheet(HTML) 13 Page - Texas Instruments |
13 / 87 page ![]() CDCM6208V1F www.ti.com SCAS943 – MAY 2015 8.15 LVPECL (High-Swing CML) Output Characteristics VDD_Yx_Yy = 1.71 V to 3.465 V, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C TO 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT-I Output frequency Integer Output Divider 1.55 800 MHz VDD_Yx Output DC coupled common mode _ VCM-DC DC coupled with 50 Ω external termination to VDD_Yx_Yy V voltage Yy – 0.4 100 Ω diff load AC coupling (See Figure 12), fOUT ≤ 250 MHz VDD_Yx_Yy ≤ 1.89 V 0.45 0.75 1.12 V VDD_Yx_Yy ≥ 2.375 V 0.6 0.8 1.12 V |VOD| Differential output voltage 100 Ω diff load AC coupling (See Figure 12), fOUT ≥ 250 MHz VDD_Yx_Yy ≤ 1.89 V 0.73 V VDD_Yx_Yy ≥ 2.375 V 0.55 0.75 1.12 V Differential output peak-to-peak VOUT 2 x |VOD| V voltage ±200 mV around crossing point 109 217 ps tR/tF Output rise/fall time 20% to 80% VOD 211 ps tslew Output rise/fall slew rate 3.7 5.1 7.3 V/ns PN-floor Phase noise floor VDD_Yx_Yy = 3.3 V (See Figure 54) –161.4 –155.8 dBc/Hz ODC Output duty cycle Not in bypass mode 47.5% 52.5% ROUT Output impedance measured from pin to VDD_Yx_Yy 50 Ω 8.16 CML Output Characteristics VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V, TA = –40°C to 85°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fOUT-I Output frequency Integer Output Divider 1.55 800 MHz Output AC coupled common VCM-AC AC coupled with 50 Ω receiver termination VDD_Yx_Yy – 0.46 V mode voltage DC coupled with 50 Ω on-chip termination Output DC coupled common VCM-DC VDD_Yx_Yy – 0.2 V mode voltage to VDD_Yx_Yy |VOD| Differential output voltage 100 Ω diff load AC coupling, (See Figure 12) 0.3 0.45 0.58 V Differential output peak-to-peak VOUT 2 x |VOD| V voltage VDDYx = 1.8 V 100 151 300 ps tR/tF Output rise/fall time 20% to 80% VDDYx = 2.5 V/3.3 V 100 143 200 ps VDD_Yx_Yy = 1.8 V –161.2 –155.8 dBc/Hz PN-floor Phase noise floor at > 5 Hz offset fOUT = 122.88 MHz VDD_Yx_Yy = 3.3 V –161.2 –153.8 dBc/Hz ODC Output duty cycle Not in bypass mode 47.5% 52.5% ROUT Output impedance measured from pin to VDD_Yx_Yy 50 Ω Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Links: CDCM6208V1F |
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