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CDCM6208V1FRGZR Datasheet(PDF) 73 Page - Texas Instruments |
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CDCM6208V1FRGZR Datasheet(HTML) 73 Page - Texas Instruments |
73 / 87 page ![]() CDCM6208V1F www.ti.com SCAS943 – MAY 2015 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains (continued) 12.1.2 Delaying VDD_Yx_Yy to Protect DSP IOs DSPs and other highly integrated processors sometimes do not permit any clock signal to be present until the DSP power supply for the corresponding IO is also present. The CDCM6208V1F allows to either sequence output clock signals by writing to the corresponding output enable bit through SPI/I2C, or alternatively it is possible to connect the DSP IO supply and the CDCM6208V1F output supply together, in which case the CDCM6208V1F output will not turn on until the DSP supply is also valid. This second implementation avoids SPI/I2C programming. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 73 Product Folder Links: CDCM6208V1F |
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