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CDCM6208V1FRGZR Datasheet(PDF) 69 Page - Texas Instruments |
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CDCM6208V1FRGZR Datasheet(HTML) 69 Page - Texas Instruments |
69 / 87 page ![]() CDCM6208V1F www.ti.com SCAS943 – MAY 2015 11.2.2.2 Jitter Considerations in ADC and DAC Systems A/D and D/A converters are sensitive to clock jitter in two ways: They are sensitive to phase noise in a particular frequency band, and also have maximum spur level requirements to achieve maximum noise floor sensitivity. The following test results were achieved connecting the CDCM6208V1F to ADC and DACs: Figure 52. IF = 60 MHz Fclk = 122.88 MHz Baseline (Lab Clk Generator) ADC: ADS62P48-49 Figure 53. IF = 60 MHz Fclk = 122.88 MHz CDCM6208V1F driving ADC Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 69 Product Folder Links: CDCM6208V1F |
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