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CDCM6208V1FRGZR Datasheet(PDF) 66 Page - Texas Instruments |
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CDCM6208V1FRGZR Datasheet(HTML) 66 Page - Texas Instruments |
66 / 87 page ![]() CDCM6208V1F SCAS943 – MAY 2015 www.ti.com 11.2.1.16.6 Output MUX on Y4 and Y5 The CDCM6208V1F device outputs Y4 and Y5 can either be used as independent fractional outputs or allow bypassing of the PLL in order to output the primary or secondary input signal directly. 11.2.1.16.7 Staggered CLK Output Powerup for Power Sequencing of a DSP DSPs are sensitive to any kind of voltage swing on unpowered input rails. To protect the DSP from long-term reliability problems, it is recommended to avoid any clock signal to the DSP until the DSP power rail is also powered up. This can be achieved in two ways using the CDCM6208V1F: 1. Digital control: Initiating a configuration of all registers so that all outputs are disabled, and then turning on outputs one by one through serial interface after each DSP rail becomes powered up accordingly. 2. Output Power supply domain control: An even easier scheme might be to connect the clock output power supply VDD_Yx to the corresponding DSP input clock supply domain. In this case, the CDCM6208V1F output will remain disabled until the DSP rails ramps up as well. Figure 49 shows the turn-on behavior. Figure 49. Sequencing the Output Turn-on Through Sequencing the Output Supplies. Output Y2 Powers Up While Output Y0 is Already Running. 66 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CDCM6208V1F |
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