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CDCM6208V1FRGZR Datasheet(PDF) 64 Page - Texas Instruments |
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CDCM6208V1FRGZR Datasheet(HTML) 64 Page - Texas Instruments |
64 / 87 page ![]() ÷ 1, 2 or 3 Pre-Scaler output clock 398-800MHz Limit: 200-400MHz ÷ 4, 5 or 6 VCO 2.39-2.55GHz 2.94-3.13GHz Pre-Scaler PS_A or PS_B FracDiv Pre Divider Reg 9.12:10 Reg 12.12:10 Reg 15.12:10 Reg 18.12:10 ÷ 1 to 256 Reg 10.11:4 Reg 13.11:4 Reg 16.11:4 Reg 19.11:4 Integer Divider Reg 3.4:0 .xxx Reg 10.3:0 + Reg 11 Reg 13.3:0 + Reg 14 Reg 16.3:0 + Reg 17 Reg 19.3:0 + Reg 20 Fractional Divider (simplified) Fractional division CDCM6208V1F SCAS943 – MAY 2015 www.ti.com 11.2.1.16.3 Integer Output Divider (IO) Each integer output divider is made up of a continuous 10-b counter. The output buffer itself contributes only little to the total device output jitter due to a low output buffer phase noise floor. The typical output phase noise floor at an output frequency of 122.88 MHz, 20 MHz offset from the carrier measures as follows: LVCMOS: -157.8 dBc/Hz, LVDS: -158 dBc/Hz, LVPECL: -158.25 dBc/Hz, HCSL: -160 dBc/Hz. Therefore, the overall contribution of the output buffer to the total jitter is approximately 50 fs-rms (12 k - 20 MHz). An actual measurement of phase noise floor with different output frequencies for one nominal until yielded the following: Table 37. Integer Output Divider (IO) fOUT LVDS (Y0) PECL (Y0) CML (Y0) HCSL (Y4) CMOS 3p3V (Y7) 737.28 MHz -154.0 dBc/Hz -154.8 dBc/Hz -154.4 dBc/Hz -153.1 dBc/Hz -150.9 dBc/Hz 368.64 MHz -157.0 dBc/Hz -155.8 dBc/Hz -156.4 dBc/Hz -153.9 dBc/Hz -153.1 dBc/Hz 184.32 MHz -157.3 dBc/Hz -158.6 dBc/Hz 158.1 dBc/Hz -154.7 dBc/Hz -156.2 dBc/Hz 92.16 MHz -161.2 dBc/Hz -161.6 dBc/Hz -161.4 dBc/Hz -155.2 dBc/Hz -159.4 dBc/Hz 46.08 MHz -162.2 dBc/Hz -165.0 dBc/Hz -163.0 dBc/Hz -154.0 dBc/Hz -162.8 dBc/Hz 11.2.1.16.4 Fractional Output Divider (FOD) The CDCM6208V1F incorporates a fractional output divider on Y[7:4], allowing these outputs to run at non- integer output divide ratios of the PLL frequencies. This feature is useful when systems require different, unrelated frequencies. The fractional output divider architecture is shown in Figure 47. Figure 47. Fractional Output Divider Principle Architecture (Simplified Graphic, not Showing Output Divider Bypass Options) The fractional output divider requires an input frequency between 400 MHz and 800 MHz, and outputs any frequency equal or less than 400 MHz (the minimum fractional output divider setting is 2). The fractional divider block has a first stage integer pre-divider followed by a fractional sigma-delta output divider block that is deep enough such as to generate any output frequency in the range of 0.78 MHz to 400 MHz from any input frequency in the range of 400 MHz to 800 MHz with a worst case frequency accuracy of no more than ±1ppm. The fractional values available are all possible 20-b representations of fractions within the following range: • 1.0 ≤ ƒracDIV ≤ 1.9375 • 2.0 ≤ ƒracDIV ≤ 3.875 • 4.0 ≤ ƒracDIV ≤ 5.875 • x.0 ≤ ƒracDIV ≤ (x + 1) + 0.875 with x being all even numbers from x = 2, 4, 6, 8, 10, ...., 254 • 254.0 ≤ ƒracDIV ≤ 255.875 • 256.0 ≤ ƒracDIV ≤ 256.99999 The CDCM6208V1F user GUI comprehends the fractional divider limitations; therefore, using the GUI to comprehend frequency planning is recommended. 64 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CDCM6208V1F |
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