CDCM6208V1FRGZR datasheet(63/87 Pages) TI1

Part #	CDCM6208V1FRGZR

Description	2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

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Manufacturer	TI1 [Texas Instruments]

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ELF

R2

C2

C1

R3

C3

CDCM6208V1F

www.ti.com

SCAS943 – MAY 2015

Figure 46. CDCM6208V1F PLL Loop Filter Topology

11.2.1.16.1

Loop Filter Component Selection

The loop filter setting and external resistor selection is important to set the PLL to best possible bandwidth and to

minimize jitter. A high bandwidth (

≥ 100 kHz) provides best input signal tracking and is therefore desired with a

clean input reference (synthesizer mode). A low bandwidth (

≤ 1 kHz) is desired if the input signal quality is

unknown (jitter cleaner mode). TI provides a software tool that makes it easy to select the right loop filter

components. C1, R2, and C2 are external loop filter components, connected to the ELF pin. The 3 rd pole of the

loop filter is device internal with R3 and C3 register selectable.

11.2.1.16.2

Device Output Signaling

LVDS-like: All outputs Y[7:0] support LVDS-like signaling. The actual output stage uses a CML structure and

drives a signal swing identical to LVDS (~350mV). The output slew rate is faster than standard LVDS for best

jitter performance. The LVDS-like outputs should be AC-coupled when interfacing to a LVDS receiver. See

reference schematic Figure 64 for an example. The supply voltage for outputs configured LVDS can be selected

freely between 1.8 V and 3.3 V.

LVPECL-like: Outputs Y[3:0] support LVPECL-like signaling. The actual output stage uses a CML structure but

drives the same signal amplitude and rise time as true emitter coupled logic output stages. The LVPECL-like

outputs should be AC-coupled, and contrary to standard PECL designs, no external termination resistor to VCC-

2V is used (fewer components for lowest BOM cost). See reference schematic Figure 64 for an example. The

supply voltage for outputs configured LVPECL-like is recommended to be 3.3 V, though even 1.8 V provides

nearly the same output swing and performance at much lower power consumption.

CML: Outputs Y[3:0] support standard CML signaling. The supply voltage for outputs configured CML can be

selected freely between 1.8 V and 3.3 V. A true CML receiver can be driven DC coupled. All other differential

receiver should connected using AC coupling. See reference schematic Figure 64 for a circuit example.

HCSL: Outputs Y[7:4] support HCSL signaling. The supply voltage for outputs configured HCSL can be selected

freely between 1.8 V and 3.3 V. HCSL is referenced to GND, and requires external 50

Ω termination to GND.

See reference schematic for an example.

CMOS: Outputs Y[7:4] support 1.8 V, 2.5 V, and 3.3 V CMOS signaling. A fast or reduced slew rate can be

selected through register programming. Each differential output port can drive one or two CMOS output signals.

Both signals are “in-phase”, meaning their phase offset is zero degrees, and not 180

˚. The output swing is set by

providing the according supply voltage (for example, if VDD_Y4=2.5 V, the output swing on Y4 will be 2.5 V

CMOS). Outputs configured for CMOS should only be terminated with a series-resistor near the device output to

preserve the full signal swing. Terminating CMOS signals with a 50

Ω resistor to GND would reduce the output

signal swing significantly.

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