CDCM6208V1FRGZR datasheet(62/87 Pages) TI1

Part #	CDCM6208V1FRGZR

Description	2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

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Manufacturer	TI1 [Texas Instruments]

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CDCM6208V1F

SCAS943 – MAY 2015

www.ti.com

all outputs in reset so that the CDCM6208V1F generates no spurious clock signals.

11.2.1.10 Reference Divider (R)

The reference (R) divider is a continuous 4-b counter (1 – 16) that is present on the primary input before the

Smart Input MUX. It is operational in the frequency range of 8 kHz to 250 MHz. The output of the R divider sets

the input frequency for the Smart MUX, and the auto switch capability of the Smart MUX can then be employed

as long as the secondary input frequency is no more than ± 20% different from the output of the R divider.

11.2.1.11 Input Divider (M)

The input (M) divider is a continuous 14-b counter (1 – 16384) that is present after the Smart Input MUX. It is

operational in the frequency range of 8 kHz to 250 MHz. The output of the M divider sets the PFD frequency to

the PLL and should be in the range of 8 kHz to 100 MHz.

11.2.1.12 Feedback Divider (N)

The feedback (N) divider is made up of cascaded 8-b counter divider (1 – 256) followed by a 10-b counter divider

(1 – 1024) that are present on the feedback path of the PLL. It is operational in the frequency range of 8 kHz to

800 MHz. The output of the N divider sets the PFD frequency to the PLL and should be in the range of 8 kHz to

100 MHz. The frequency out of the first divider is required to be less than or equal to 200 MHz to ensure proper

operation.

11.2.1.13 Prescaler Dividers (PS_A, PS_B)

The prescaler (PS) dividers are fed by the output of the VCO and are distributed to the output dividers (PS_A to

the dividers for Outputs 0, 1, 4, and 5 and PS_B to the dividers for Outputs 2, 3, 6, and 7. PS_A also completes

the PLL as it also drives the input of the Feedback Divider (N).

11.2.1.14 Phase Frequency Detector (PFD)

The PFD takes inputs from the Smart Input MUX output and the feedback divider output and produces an output

that is dependent on the phase and frequency difference between the two inputs. The allowable range of

frequencies at the inputs of the PFD is from 8 kHz to 100 MHz.

11.2.1.15 Charge Pump (CP)

The charge pump is controlled by the PFD which dictates either to pump up or down in order to charge or

discharge the integrating section of the on-chip loop filter. The integrated and filtered charge pump current is then

converted to a voltage that drives the control voltage node of the internal VCO through the loop filter. The range

of the charge pump current is from 500 µA to 4 mA.

11.2.1.16 Programmable Loop Filter

The on-chip PLL supports a partially internal and partially external loop filter configuration for all PLL loop

bandwidths where the passive external components C1, C2, and R2 are connected to the ELF pin as shown in

Figure 46 to achieve PLL loop bandwidths from 400 kHz down to 10 Hz.

62

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