CDCM6208V1FRGZR datasheet(60/87 Pages) TI1

Part #	CDCM6208V1FRGZR

Description	2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

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"

=3.5%

250ns

140ns

Step 7

Time from PLL Lock

to LOCK signal asserting high on STATUS0 = 78Us

CDCM6208V1F

SCAS943 – MAY 2015

www.ti.com

Figure 44. PLL Lock Behavior (Step 6)

11.2.1.7 Input Mux and Smart Input Mux

The Smart Input MUX supports auto-switching and manual-switching using control pin (and through register).

The Smart Input MUX is designed such that glitches created during switching in both auto and manual modes

are suppressed at the MUX output.

Table 36. Input Mux Selection

REGISTER 4 BIT

SI_MODE1

REGISTER 4 BIT 12

REF_SEL

13SMUX_MODE_SE

SELECTED INPUT

PIN NO. 47

SMUX_REF_SEL

PIN NO. 6

L

Auto Select Priority is given to Primary

0

X

Reference input.

0

Primary input

input select through

1

0 (SPI/I2C mode)

SPI/I2C

1

Secondary input

1

0

Primary input

input select through

1

external pin

1

Secondary input

0

Primary or Auto (see Table 5)

1 (pin mode)

not available

1

Secondary or Auto (see Table 5)

Example 1:An application desired to auto-select the clock reference in SPI/I2C mode. During production testing

however, the system needs to force the device to use the primary followed by the secondary input. The settings

would be as follows:

1. Tie REF_SEL pin always high

2. For primary clock input testing, use R4[13:12] = 10

3. For secondary clock input testing, set R4[13:12] = 11.

4. For the auto-mux setting in the final product shipment, set R3[13:12]=01 or 00

Example 2: The application wants to select the clock input manually without programming SPI/I2C. In this case,

program R4[13:12] = 11, and select primary or secondary input by toggling REF_SEL low or high.

60

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