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CDCM6208V1FRGZR Datasheet(PDF) 55 Page - Texas Instruments |
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CDCM6208V1FRGZR Datasheet(HTML) 55 Page - Texas Instruments |
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55 / 87 page  (c) (PIN Mode) (b) (SPI/I2C Host Mode) 50k #44 (RESET) DVDD CDCM6208 50k #44 (RESET) DVDD CDCM6208 GPO 50k #44 (PWR) DVDD CDCM6208 RPD if I/O power = 1.8V: RPD=0-Ohm if I/O power=3.3V: RPD=open (a) (SPI/I2C Host mode) 5k Host Controller CDCM6208V1F www.ti.com SCAS943 – MAY 2015 Typical Applications (continued) 11.2.1.3 Configuring the RESETN Pin Figure 39 shows two typical applications examples of the RESETN pin. Figure 39. RESETN/PWR Pin Configurations Figure 39 (a) SPI / I2C mode only: shows the RESETN pin connected to a digital device that controls device reset. The resistor and capacitor combination ensure reset is held low even if the CDCM6208V1F is powered up before the host controller output signal is valid. Figure 39 (b) SPI / I2C mode only:shows a configuration in which the user wishes to introduce a delay between the time that the system applies power to the device and the device exiting reset. If the user does not use a capacitor, then the device effectively ignores the state of the RESETN pin. Figure 39 (c) Pin mode only: shows a configuration useful if the device is used in Pin Mode. Here device pin number 44 becomes the PWR input. An external pull down resistor can be used to pull this pin down. If the resistor is not installed, the pin is internally pulled high. Copyright © 2015, Texas Instruments Incorporated Submit Documentation Feedback 55 Product Folder Links: CDCM6208V1F |
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