CDCM6208V1FRGZR datasheet(51/87 Pages) TI1

Part #	CDCM6208V1FRGZR

Description	2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

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Manufacturer	TI1 [Texas Instruments]

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CDCM6208V1F

www.ti.com

SCAS943 – MAY 2015

Table 32. Register 21 (Read Only)

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

15

RESERVED

This bit will read a 0

14

RESERVED

This bit will read a 0

13

RESERVED

This bit will read a 0

12

RESERVED

This bit will read a 0

11

RESERVED

This bit will read a 0

10

RESERVED

This bit will read a 0

9

RESERVED

This bit will read a 0

8

RESERVED

This bit will read a 0

7

RESERVED

This bit will read a 0

6

RESERVED

This bit will read a 0

5

RESERVED

This bit will read a 0

4

RESERVED

This bit will read a 0

3

RESERVED

This bit will read a 0

Indicates unlock status for PLL (digital):

0

→ PLL locked

1

→ PLL unlocked

2

PLL_UNLOCK

Note: the external output signal on Status 0 or Status 1 uses a

reversed logic, and indicates "lock" with a VOH signal and unlock

with a VOL signaling level.

Device Status

Loss of reference input observed at input Smart MUX output in

Monitoring

observation window for PLL:

1

LOS_REF

0

→ Reference input present

1

→ Loss of reference input

Indicates Reference Selected for PLL:

0

SEL_REF

0

→ Primary

1

→ Secondary

Table 33. Register 40 (Read Only)

BIT

BIT NAME

RELATED BLOCK

DESCRIPTION/FUNCTION

15

RESERVED

Ignore

14

RESERVED

Ignore

13

RESERVED

Ignore

12

RESERVED

Ignore

11

RESERVED

Ignore

10

RESERVED

Ignore

9

RESERVED

Ignore

8

RESERVED

Ignore

7

RESERVED

Ignore

6

RESERVED

Ignore

Indicates the device version (Read only):

5:3

VCO_VERSION

000

→ CDCM6208V1F

Device Information

Indicates the silicon die revision (Read only):

2:0

DIE_REVISION

00X --> Engineering Prototypes

010 --> Production Material

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