CDCM6208V1FRGZR datasheet(36/87 Pages) TI1

Part #	CDCM6208V1FRGZR

Description	2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

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5

4

3

2

Reg05

Register Number (s)

Bit Number(s)

R05 .2

CDCM6208V1F

SCAS943 – MAY 2015

www.ti.com

10.4.5.1 Register File Reference Convention

Figure 29 shows the method this document employs to refer to an individual register bit or a grouping of register

bits. If a drawing or text references an individual bit, the format is to specify the register number first and the bit

number second. The CDCM6208V1F contains 21 registers that are 16 bits wide. The register addresses and the

bit positions both begin with the number zero (0). A period separates the register address and bit address. The

first bit in the register file is address 'R0.0' meaning that it is located in Register 0 and is bit position 0. The last

bit in the register file is address R31.15 referring to the 16thbit of register address 31 (the 32ndregister in the

device

Figure 29. CDCM6208V1F Register Reference Format

36

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