CDCM6208V1FRGZR datasheet(35/87 Pages) TI1

Part #	CDCM6208V1FRGZR

Description	2:8 Clock Generator, Jitter Cleaner with Fractional Dividers

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Manufacturer	TI1 [Texas Instruments]

Direct Link	http://www.ti.com

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Device

Control

And

Status

STATUS0

STATUS1/PIN0

PDN

RESETN/PWR

SCL/PIN4

SDI/SDA/PIN1

SDO/AD0/PIN2

SCS/AD1/PIN3

SI_MODE0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg 0

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg1

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg2

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg3

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg 20

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg 21

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg 22

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg 23

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg30

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

Reg31

REGISTER SPACE

Device

Hardware

SPI/

I2C

Port

Control/

Status

Pins

SPI: SI_MODE[1:0]=00;

I2C: SI_MODE[1:0]=01;

Pin Mode: SI_MODE[1:0]=10

SI_MODE1

Comm

Select

CDCM6208V1F

www.ti.com

SCAS943 – MAY 2015

NOTE

It is recommended to assert only one out of the three register bits for each of the status

pins. For example, to monitor the PLL lock status on STATUS0 and the selected reference

clock sources on STATUS1 output, the device register settings would be Q3.12 = Q3.7 =

1 and Q3.11 = Q3.10 = Q3.9 = Q3.8 = 0. If a status pin is unused, it is recommended to

set the according 3 register bits to zero (e.g. Q3[12:9] = 0 for STATUS0 = 0). If more than

one bit is enabled for each STATUS signal, the function becomes OR'ed. For example, if

Q3.11 = Q3.10 = 1 and Q3.12 = 0, the STATUS0 output would be high either if the device

goes out of lock or the selected reference clock signal is lost.

10.4.4 PLL Lock Detect

The PLL lock detection circuit is a digital detection circuit which detects any frequency error, even a single cycle

slip. The PLL unlock is signalized when a certain number of cycle slips have been exceeded, at which point the

counter is reset. A frequency error of 2% will cause PLL unlock to stay low. A 0.5% frequency error shows up as

toggling the PLL lock output with roughly 50% duty cycle at roughly 1/1000 th of the PFD update frequency to the

device. A frequency error of 1ppm would show up as rare toggling low for a duration of approximately 1000 PFD

update clock cycles. If the system plans using PLL lock to toggle a system reset, then consider adding an RC

filter on the PLL LOCK output (Status 1 or Status 0) to avoid rare cycle slips from triggering an entire system

reset.

10.4.5 Interface and Control

The host (DSP, Microcontroller, FPGA, etc) configures and monitors the CDCM6208V1F via the SPI or I2C port.

The host reads and writes to a collection of control/status bits called the register file. Typically, a hardware block

is controlled and monitored via a specific grouping of bits located within the register file. The host controls and

monitors certain device-wide critical parameters directly, via control/status pins. In the absence of a host, the

CDCM6208V1F can be configured to operate in pin mode where the control pins [PIN0-PIN4] can be set

appropriately to generate the necessary clock outputs out of the device.

Figure 28. CDCM6208V1F Interface and Control Block

Within this register space, there are certain bits that have read/write access. Other bits are read-only (an attempt

to write to a read only bit will not change the state of the bit).

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