5,0mm(min)

1,2mm(typ)

0,33mm(typ)

CDCLVP2108

SCAS878C – MAY 2009 – REVISED JANUARY 2016

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11 Layout

11.1 Layout Guidelines

Power consumption of the CDCLVP2108 can be high enough to require attention to thermal management. For

reliability and performance reasons, the die temperature must be limited to a maximum of 125°C. That is, as an

The device package has an exposed pad that provides the primary heat removal path to the printed circuit board

(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a

ground plane must be incorporated into the PCB within the footprint of the package. The exposed pad must be

soldered down to ensure adequate heat conduction out of the package. Figure 24 shows a recommended land

and via pattern.

11.2 Layout Example

Figure 24. Recommended PCB Layout

11.3 Thermal Considerations

The CDCLVP2108 supports high temperatures on the printed circuit board (PCB) measured at the thermal pad.

The system designer must ensure that the maximum junction temperature is not exceeded.

system designer to measure the board temperature with a fine gauge thermocouple and back calculate the

junction temperature using Equation 1. Note that

is dissipated by the PCB. Further information can be found at SPRA953 and SLUA566.

(1)

Example:

Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:

termination resistors)

for further details)

125°C is not violated)

22

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