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CDCLVP2108 Datasheet(PDF) 20 Page - Texas Instruments

Part # CDCLVP2108
Description  16-LVPECL Output, High-Performance Clock Buffer
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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CDCLVP2108 Datasheet(HTML) 20 Page - Texas Instruments

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CDCLVP2108
SCAS878C – MAY 2009 – REVISED JANUARY 2016
www.ti.com
Typical Application (continued)
The FPGA requires external AC coupling but has internal termination. Again, 86-
Ω emitter resistors are
placed near the CDCLVP2108, and 0.1
μF are placed to provide AC coupling. Similarly, the CPU is internally
terminated and requires external AC coupling capacitors.
9.2.2 Detailed Design Procedure
Refer to Input Termination for proper input terminations, dependent on single ended or differential inputs.
Refer to LVPECL Output Termination for output termination schemes depending on the receiver application.
Unused outputs can be left floating.
In Figure 20, the PHY, ASIC, and FPGA/CPU require different schemes. Power supply filtering and bypassing is
critical for low-noise applications.
See Power Supply Recommendations for recommended filtering techniques. A reference layout is provided on
the CDCLVP2108 Evaluation Module, Low Additive Phase Noise Clock Buffer Evaluation Board User's Guide
(SCAU038).
9.2.3 Application Curves
Reference signal is low-noise Crystek XO CPRO33.156.25
32 fs, RMS
10 kHz to 20 MHz
57 fs, RMS
10 kHz to 20 MHz
Figure 21. CDCLVP21xx Reference Phase Noise
Figure 22. CDCLVP21xx Output Phase Noise
The low additive noise of the CDCLVP2108 can be shown in this line-card application. The low noise 156.25
MHz XO with 32-fs, RMS jitter drives the CDCLVP2108, resulting in 57 fs, RMS when integrated from 10 kHz to
20 MHz. The resultant additive jitter is a low 47 fs, RMS for this configuration.
20
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Product Folder Links: CDCLVP2108


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