2.5 V

PRIREF_P

PRIREF_N

96

105

2.5 V

156.25 MHz LVPECL

from backplane

SECREF_P

CDCLVP21xx

1k

1k

2.5 V

86

86

PHY

SECREF_N

100

ASIC

250

2.5 V

62.5

86

86

FPGA

100

86

86

CPU

100

156.25 MHz LVCMOS

Oscillator

CDCLVP2108

www.ti.com

SCAS878C – MAY 2009 – REVISED JANUARY 2016

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

The CDCLVP2108 is a low additive jitter LVPECL fan-out buffer that can generate two copies each of two

independent LVPECL, LVDS, or LVCMOS inputs. The CDCLVP2108 can accept reference clock frequencies up

to 2 GHz while providing low output skew.

9.2 Typical Application

Figure 20 shows a fan-out buffer for line-card application.

Figure 20. CDCLVP2108 Typical Application

9.2.1 Design Requirements

The CDCLVP2108 shown in Figure 20 is configured to be able to select two inputs: a 156.25-MHz LVPECL clock

from the backplane, or a secondary 156.25-MHz LVCMOS 2.5-V oscillator. Either signal can be then fanned out

to desired devices, as shown.

The configuration example is driving 4 LVPECL receivers in a line-card application with the following properties:

•

The PHY device has internal AC coupling and appropriate termination and biasing. The CDCLVP2108 must

be provided with 86-

Ω emitter resistors near the driver for proper operation.

•

The ASIC is capable of DC coupling with a 2.5-V LVPECL driver such as the CDCLVP2108. This ASIC

features internal termination so no additional components are needed.

Copyright © 2009–2016, Texas Instruments Incorporated

Submit Documentation Feedback

19

Product Folder Links: CDCLVP2108