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CDCL1810RGZR Datasheet(PDF) 12 Page - Texas Instruments

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Part # CDCL1810RGZR
Description  Output, High-Performance Clock Distributor
PDF  33 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CDCL1810RGZR Datasheet(HTML) 12 Page - Texas Instruments

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RP
C
F
SCL
SDA
CDCL1810
(Slave)
Master
RP
CDCL1810
SLLS781D – FEBRUARY 2007 – REVISED NOVEMBER 2014
www.ti.com
9.4 SDA/SCL Connections Recommendations
The serial interface inputs don’t have glitch suppression circuit. So, any noises or glitches at serial input lines
may cause programming error. The serial interface lines should be routed in such a way that the lines would
have minimum noise impact from the surroundings.
Figure 6 is recommended to improve the interconnections.
Figure 6. Serial Interface Connections
Lower RP resistor value (around 1 kΩ) should be chosen so that signals will have faster rise time. A capacitor
can be connected to SCL line to ground which will act as a filter.
An I2C level translator will help to overcome the noises issue.
9.5 Device Functional Modes
The device is designed to operate from an input voltage supply of 1.8 V. In the default power on reset, all device
outputs are enabled and the dividers P0 and P1 are set to 1.
12
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Product Folder Links: CDCL1810


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