CDCL1810RGZR datasheet(17/33 Pages) TI1

Part #	CDCL1810RGZR

Description	Output, High-Performance Clock Distributor

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Manufacturer	TI1 [Texas Instruments]

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CDCL1810

www.ti.com

SLLS781D – FEBRUARY 2007 – REVISED NOVEMBER 2014

9.7.7 Byte 6:

POWER UP

REFERENCE

BIT

BIT NAME

DESCRIPTION/FUNCTION

TYPE

CONDITION

TO

7

ENDRV3

YP[3], YN[3] enable; if 0 output is disabled

R/W

1

6

ENDRV2

YP[2], YN[2] enable; if 0 output is disabled

R/W

1

5

ENDRV1

YP[1], YN[1] enable; if 0 output is disabled

R/W

1

4

ENDRV0

YP[0], YN[0] enable; if 0 output is disabled

R/W

1

3

RES

Reserved

R/W

0

2

RES

Reserved

R/W

0

1

RES

Reserved

R/W

0

RES

Reserved

R/W

0

Table 3. Divide Ratio Settings for Post-Divider P0 or P1

DIVIDE

SELP1[3] or

SELP1[2] or

SELP1[1] or

SELP1[0] or

NOTES

RATIO

SELP0[3]

SELP0[2]

SELP0[1]

SELP0[0]

1

0

Default

2

0

1

4

0

1

0

5

0

1

8

0

1

0

10

0

1

0

1

16

0

1

0

20

0

1

32

1

0

40

1

0

1

80

1

0

1

0

Table 4. Phase Settings for Divide Ratio = 5, 10, 20, 40, 80

WITH PH0[4:0] = 00000

DIVIDE

PHASE LEAD

PH1

NOTES

RATIO

(RADIAN)

[4]

[3]

[2]

[1]

[0]

5

X

0

Phase setting not available

10

X

0

X

0

X

1

X

(2

π/2)

20

X

0

X

0

X

0

1

X

(2

π/4)

X

1

0

X

2(2

π/4)

X

1

X

3(2

π/4)

40

X

0

X

0

X

0

1

X

(2

π/8)

X

0

1

0

X

2(2

π/8)

X

0

1

X

3(2

π/8)

X

1

0

X

4(2

π/8)

X

1

0

1

X

5(2

π/8)

X

1

0

X

6(2

π/8)

X

1

X

7(2

π/8)

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