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CDCL1810RGZR Datasheet(PDF) 16 Page - Texas Instruments |
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CDCL1810RGZR Datasheet(HTML) 16 Page - Texas Instruments |
16 / 33 page ![]() CDCL1810 SLLS781D – FEBRUARY 2007 – REVISED NOVEMBER 2014 www.ti.com 9.7.4 Byte 3: POWER UP REFERENCE BIT BIT NAME DESCRIPTION/FUNCTION TYPE CONDITION TO 7 RES Reserved R/W 0 6 RES Reserved R/W 0 5 RES Reserved R/W 0 4 PH0[4] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4, Table 5 3 PH0[3] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4, Table 5 2 PH0[2] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4, Table 5 1 PH0[1] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4, Table 5 0 PH0[0] Phase select for YP[4:0] and YN[4:0] R/W 0 Table 4, Table 5 9.7.5 Byte 4: POWER UP REFERENCE BIT BIT NAME DESCRIPTION/FUNCTION TYPE CONDITION TO 7 RES Reserved R/W 0 6 RES Reserved R/W 0 5 ENP0 Post-divider P0 enable. If 0, output YP[4:0] and YN[4:0] are disabled R/W 1 4 RES Reserved R/W 1 3 SELP0[3] Divide ratio select for post-divider P0 R/W 0 Table 3 2 SELP0[2] Divide ratio select for post-divider P0 R/W 0 Table 3 1 SELP0[1] Divide ratio select for post-divider P0 R/W 0 Table 3 0 SELP0[0] Divide ratio select for post-divider P0 R/W 0 Table 3 9.7.6 Byte 5: POWER UP REFERENCE BIT BIT NAME DESCRIPTION/FUNCTION TYPE CONDITION TO 7 EN Chip enable; if 0 chip is in Iddq mode R/W 1 6 RES Reserved R 1 5 ENDRV9 YP[9], YN[9] enable; if 0 output is disabled R/W 1 4 ENDRV8 YP[8], YN[8] enable; if 0 output is disabled R/W 1 3 ENDRV7 YP[7], YN[7] enable; if 0 output is disabled R/W 1 2 ENDRV6 YP[6], YN[6] enable; if 0 output is disabled R/W 1 1 ENDRV5 YP[5], YN[5] enable; if 0 output is disabled R/W 1 0 ENDRV4 YP[4], YN[4] enable; if 0 output is disabled R/W 1 16 Submit Documentation Feedback Copyright © 2007–2014, Texas Instruments Incorporated Product Folder Links: CDCL1810 |
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