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CDCE62005 Datasheet(PDF) 15 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 85 page  Interface & Control REF_SEL Power_Down SYNC EEPROM (Default Configuration) Device Hardware SPI_LE SPI_CLK SPI_MISO SPI_MOSI Register 0 Static RAM (Device Registers) Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Register 8 Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 CDCE62005 www.ti.com SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 Functional Block Diagrams (continued) 8.2.1 Interface and Control Block The CDCE62005 is a highly flexible and configurable architecture and as such contains a number of registers so that the user may specify device operation. The contents of nine 28-bit wide registers implemented in static RAM determine device configuration at all times. On power-up, the CDCE62005 copies the contents of the EEPROM into the RAM and the device begins operation based on the default configuration stored in the EEPROM. Systems that do not have a host system to communicate with the CDCE62005 use this method for device configuration. The CDCE62005 provides the ability to lock the EEPROM; enabling the designer to implement a fault tolerant design. After power-up, the host system may overwrite the contents of the RAM via the SPI (Serial Peripheral Interface) port. This enables the configuration and reconfiguration of the CDCE62005 during system operation. Finally, the device offers the ability to copy the contents of the RAM into EEPROM, if the EEPROM is unlocked. Figure 11. CDCE62005 Interface and Control Block Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: CDCE62005 |
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