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CDCE62005 Datasheet(PDF) 14 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 85 page  Output Divider 0 U0P U0N U1P U1N U2P U2N U3P U3N U4P U4N PFD / CP /1:/2:HiZ /1:/2:HiZ Prescaler Feedback Divder Input Divider Reference Divider AUX OUT PRI_REF SEC_REF XTAL / AUX IN EEPROM Interface & Control REF_SEL Power_down SYNC SPI_LE SPI_CLK SPI_MISO SPI_MOSI EXT_LFP EXT_LFN Output Divider 1 Output Divider 2 Output Divider 3 Output Divider 4 CDCE62005 SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 www.ti.com 8 Detailed Description 8.1 Overview The CDCE62005 comprises of four primary blocks: the interface and control block, the input block, the output block, and the synthesizer block. In order to determine which settings are appropriate for any specific combination of input/output frequencies, a basic understanding of these blocks is required. The interface and control block determines the state of the CDCE62005 at power-up based on the contents of the on-chip EEPROM. In addition to the EEPROM, the SPI port is available to configure the CDCE62005 by writing directly to the device registers after power-up. The input block selects which of the three input ports is available for use by the synthesizer block and buffers all clock inputs. The output block provides five separate clock channels that are fully programmable and configurable to select and condition one of four internal clock sources. The synthesizer block multiplies and filters the input clock selected by the input block. NOTE This section provides a high-level description of the features of the CDCE62005 for purpose of understanding its capabilities. For a complete description of device registers and I/O, please refer to Device Configuration and Register Maps. 8.2 Functional Block Diagrams 14 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: CDCE62005 |
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