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CDCE62005 Datasheet(PDF) 11 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 85 page  Bit30 Bit0 = 0 Bit1 Bit2 Bit31 t2 t3 t4 t5 t8 t7 t6 t9 SPI_CLK SPI_MOSI SPI_MISO SPI_LE Bit0 Bit1 Bit30 Bit29 t1 t2 t3 t4 t5 t6 t7 Bit31 SPI_CLK SPI_MOSI SPI_LE CDCE62005 www.ti.com SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 6.5 Timing Requirements over recommended ranges of supply voltage, load and operating free air temperature (unless otherwise noted) MIN NOM MAX UNIT PRI_REF/SEC_REF REQUIREMENTS Maximum Clock Frequency Applied to PRI_REF and SEC_REF in fan-out mode 1500 MHz Maximum Clock Frequency Applied to Smart Multiplexer input Divider 500 MHz fmax Maximum Clock Frequency Applied to Reference Divider 250 MHz For Single ended Inputs ( LVCMOS) on PRI_REF and SEC_REF 250 MHz Duty cycle of PRI_REF or SEC_REF at VCC / 2 40% 60% Input Clock Slew Rate (Differential and Single ended) 1 V/ns Power_Down, SYNC, REF_SEL REQUIREMENTS tr/ tf Rise and fall time of the Power_Down, SYNC, REF_SEL signal from 20% to 80% of VCC 4 ns 6.6 SPI Bus Timing Characteristics MIN NOM MAX UNIT fClock Clock Frequency for the 20 MHz SPI_CLK t1 SPI_LE to SPI_CLK setup time See Figure 1 and Figure 2 10 ns t2 SPI_MOSI to SPI_CLK setup See Figure 1 and Figure 2 10 ns time t3 SPI_MOSI to SPI_CLK hold See Figure 1 and Figure 2 10 ns time t4 SPI_CLK high duration See Figure 1 and Figure 2 25 ns t5 SPI_CLK low duration See Figure 1 and Figure 2 25 ns t6 SPI_CLK to SPI_LE Hold time See Figure 1 and Figure 2 10 ns t7 SPI_LE Pulse Width See Figure 1 and Figure 2 20 ns t8 SPI_CLK to MISO data valid See Figure 2 10 ns t9 SPI_LE to SPI_MISO Data Valid See Figure 2 10 ns Figure 1. Timing Diagram for SPI Write Command Figure 2. Timing Diagram for SPI Read Command Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: CDCE62005 |
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