 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
CDCE62005 Datasheet(PDF) 71 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
CDCE62005 Datasheet(HTML) 71 Page - Texas Instruments |
|
|
71 / 85 page  CDCE62005 www.ti.com SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 Typical Application (continued) 9.2.2 Detailed Design Procedure Step 1. From Figure 47, it can be inferred that the relationship between the output frequency and the input frequency is described by these equations, where: FVCO = FOUT ´ P ´ N (17) provided that: 80 kHz < (FIN/M) < 40 MHz (18) and: 1750 MHz < (FOUT ´ P ´ N) < 2350 MHz (19) Step 2. Keep in mind the following while satisfying the equations in Step 1: • The P divider can be chosen to be 1, 2, 3, 4, 5, up to 80 • The internal VCO range is from 1.75 GHz to 2.35 GHz • The input (M) and prescaler (N) dividers can be chosen from Table 22 and Table 26. • The FB divider can be chosen from the values in Table 23 and Table 24. Step 3. Given multiple desired output frequencies and the input frequency, the first step would be to establish M, N, and FB divider values for different P divider settings to satisfy these equations: FIN = FOUT1 x (M x P1) / (N x FB) (20) FIN = FOUT2 x (M x P2) / (N x FB) (21) FIN = FOUT3 x (M x P3) / (N x FB) (22) FIN = FOUT4 x (M x P4) / (N x FB) (23) FIN = FOUT5 x (M x P5) / (N x FB) (24) (FVCO/ N) = FOUT1 x P1 = FOUT2 x P2 = FOUT3 x P3 = FOUT4 x P4 = FOUT5 x P5 (25) Such that these parameters are valid: • The common PFD frequency is always less than 40 MHz. • The VCXO frequency is the same for deriving all outputs. Using the example to derive these outputs, it can be seen that there is not an output divider (P5) that will generate a 25-MHz output. However, the output MUX value of output 5 can be chosen to directly bypass the 25- MHz input clock to output 5. Therefore, in order to use a common VCO frequency, the P dividers to be used are: • P1 = 4 • P2 = 4 • P3 = 5 • P4 = 5 • P5 = 1 The common VCO frequency is 1875 MHz and is VCO1. The output MUX for outputs 1 to 4 are set to the PLL/VCO outputs. Moreover, the FB divider to be used is: FB = 100 (26) The N divider to be used is: N = 3 (27) These values ensure that the (FIN/M) ratio is within 40 MHz and is set at 6.25 MHz. Thus, the M divider to be used is: M = 4 (28) Figure 47 illustrates this configuration. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 71 Product Folder Links: CDCE62005 |
Similar Part No. - CDCE62005 |
|
Similar Description - CDCE62005 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
