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CDCE62005 Datasheet(PDF) 67 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 67 Page - Texas Instruments |
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67 / 85 page  CDCE62005 www.ti.com SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 8.6.7 Device Registers: Register 6 Address 0x06 Table 46. CDCE62005 Register 6 Bit Definitions RAM BIT BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION 0 SELVCO VCO Core VCO Select, 0:VCO1(low range), 1:VCO2(high range) EEPROM 1 SELPRESCA VCO Core EEPROM PRESCALER Setting. 2 SELPRESCB VCO Core EEPROM 3 SELFBDIV0 VCO Core EEPROM 4 SELFBDIV1 VCO Core EEPROM 5 SELFBDIV2 VCO Core EEPROM 6 SELFBDIV3 VCO Core EEPROM FEEDBACK DIVIDER Setting 7 SELFBDIV4 VCO Core EEPROM 8 SELFBDIV5 VCO Core EEPROM 9 SELFBDIV6 VCO Core EEPROM 10 SELFBDIV7 VCO Core EEPROM 11 RESERVED Must be set to 0 EEPROM If Set to Secondary Input Buffer Internal Termination Enabled 12 SEC_TERMSEL Input Buffers EEPROM If set to 1 Secondary Internal Termination circuitry Disabled 13 SELBPDIV0 VCO Core EEPROM 14 SELBPDIV1 VCO Core BYPASS DIVIDER Setting (6 settings + Disable + Enable) EEPROM 15 SELBPDIV2 VCO Core EEPROM 16 ICPSEL0 VCO Core EEPROM 17 ICPSEL1 VCO Core EEPROM CHARGE PUMP Current Select (see Table 27) 18 ICPSEL2 VCO Core EEPROM 19 ICPSEL3 VCO Core EEPROM 20 SYNC_MODE2 VCO Core When set to 0, outputs are synchronized to the reference input on the low-to-high pulse on SYNC pin or EEPROM bit. When set to 1, outputs are synchronized to the SYNC low-to-high pulse 21 CPPULSEWIDTH VCO Core If set to 1=wide pulse, 0=narrow pulse EEPROM Enable VCO Calibration Command. To execute this command a rising edge must be generated (that is, 22 ENCAL VCO Core Write a LOW followed by a high to this bit location). This will initiate a VCO calibration sequence only if EEPROM Calibration Mode = Manual Mode (that is, Register 6 bit 27 is HIGH). 23 RESERVED Must be set to 0 EEPROM 24 AUXOUTEN Output AUX Enable Auxiliary Output when set to 1. EEPROM Select the Output that will driving the AUX Output; 25 AUXFEEDSEL Output AUX EEPROM Low for Selecting Output Divider 2 and High for Selecting Output Divider 3 When Set to 1 External Loop filter is used. 26 EXLFSEL VCO Core EEPROM When Set to 0 Internal Loop Filter is used. 1: Calibration Mode = Manual Mode. In this mode, a calibration will be initiated if a rising edge is asserted on ENCAL (Register 6 Bit 22). 27 ENCAL_MODE PLL Calibration EEPROM 0: Calibration Mode = Startup Mode. Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback 67 Product Folder Links: CDCE62005 |
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