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CDCE62005 Datasheet(PDF) 66 Page - Texas Instruments |
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CDCE62005 Datasheet(HTML) 66 Page - Texas Instruments |
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66 / 85 page  CDCE62005 SCAS862F – NOVEMBER 2008 – REVISED JANUARY 2015 www.ti.com 8.6.6 Device Registers: Register 5 Address 0x05 Table 45. CDCE62005 Register 5 Bit Definitions RAM BIT NAME RELATED BLOCK DESCRIPTION/FUNCTION BIT 0 INBUFSELX INBUFSELX Input Buffer Select (LVPECL,LVDS or LVCMOS) EEPROM Reg5[1:0]=00=LVCMOS 1 INBUFSELY INBUFSELY EEPROM Reg5[1:0]=01=reserved Reg5[1:0]=10=LVPECL Reg5[1:0]=11=LVDS 2 PRISEL When EECLKSEL = 1; EEPROM Bit (2,3,4) 100 – PRISEL, 010 – SECSEL , 001 – AUXSEL 3 SECSEL EEPROM Smart MUX 110 – Auto Select (PRI then SEC) 111 – Auto Select (PRI then SEC and then AUX) 4 AUXSEL (1) EEPROM When EECLKSEL = 0, REF_SEL pin determines the Reference Input to the Smart Mux circuitry. If EEPROM Clock Select Input is set to 1 The Clock selections follows internal EEPROM settings and ignores 5 EECLKSEL Smart MUX REF_SEL Pin status, when Set to 0 REF_SEL is used to control the Mux, Auto Select Function is not EEPROM available and AUXSEL is not available. 6 ACDCSEL Input Buffers If set to 1 DC Termination, If set to 0 AC Termination EEPROM 7 HYSTEN Input Buffers If set to 1 Input Buffers Hysteresis Enabled. It is not recommended that Hysteresis be disabled. EEPROM If set to 0 Primary Input Buffer Internal Termination Enabled 8 PRI_TERMSEL Input Buffers EEPROM If set to 1 Primary Internal Termination circuitry Disabled 9 PRIINVBB Input Buffers If set to 0 Primary Input Negative Pin Biased with Internal VBB Voltage. EEPROM 10 SECINVBB Input Buffers If set to 0 Secondary Input Negative Pin Biased with Internal VBB Voltage EEPROM 11 FAILSAFE Input Buffers If set to 1 Fail Safe is Enabled for all Input Buffers configured as LVDS, DC Coupling only. EEPROM 12 RESERVED Must be set to 0 EEPROM 13 RESERVED Must be set to 0 EEPROM 14 SELINDIV0 VCO Core EEPROM 15 SELINDIV1 VCO Core EEPROM 16 SELINDIV2 VCO Core EEPROM 17 SELINDIV3 VCO Core EEPROM INPUT DIVIDER Settings 18 SELINDIV4 VCO Core EEPROM 19 SELINDIV5 VCO Core EEPROM 20 SELINDIV6 VCO Core EEPROM 21 SELINDIV7 VCO Core EEPROM 22 LOCKW(0) PLL Lock See Table 34 EEPROM 23 LOCKW(1) EEPROM 24 LOCKW(2) EEPROM 25 LOCKW(3) EEPROM Number of coherent lock events. If set to 0 it triggers after the first lock detection if set to 1 it triggers lock 26 LOCKDET PLL Lock EEPROM after 64 PFD cycles of lock detections. 27 ADLOCK PLL Lock Selects Digital PLL_LOCK 0 ,Selects Analog PLL_LOCK 1 EEPROM (1) If the AUXSEL bit is set to 1 , a crystal must be connected to the AUXIN input properly (see the Crystal Input Interface section). 66 Submit Documentation Feedback Copyright © 2008–2015, Texas Instruments Incorporated Product Folder Links: CDCE62005 |
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